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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:44:28 09/23/2011 
-- Design Name: 
-- Module Name:    multiplier - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier is
    Port ( Q : in  STD_LOGIC_VECTOR (3 downto 0);
           M : in  STD_LOGIC_VECTOR (3 downto 0);
           P : out  STD_LOGIC_VECTOR (7 downto 0));
end multiplier;

architecture Behavioral of multiplier is

Signal c0,caryout,caryout1,caryout2,
caryout4,caryout5,caryout6,caryout8,
caryout9,caryout10,faout1,faout2,
faout3,faout4,faout5,faout6,stg1cary,stg2cary:std_logic;

COMPONENT mulbotblk
	PORT( PPi : in  STD_LOGIC;
           mk : in  STD_LOGIC;
           q : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
			  OP: out STD_logic);
END COMPONENT;
COMPONENT multopblk
Port ( mk1 : in  STD_LOGIC;
           mk : in  STD_LOGIC;
           q0 : in  STD_LOGIC;
           q1 : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           cout : out  STD_LOGIC;
           OP : out  STD_LOGIC);
end COMPONENT;


begin
c0<='0';
P(0)<=M(0) and Q(0);


stage0:multopblk PORT MAP(M(1),M(0),Q(0),Q(1),c0,caryout,P(1));
stage1:multopblk PORT MAP(M(2),M(1),Q(0),Q(1),caryout,caryout1,faout1);
stage2:multopblk PORT MAP(M(3),M(2),Q(0),Q(1),caryout1,caryout2,faout2);
stage3:multopblk PORT MAP(c0,M(3),Q(0),Q(1),caryout2,stg1cary,faout3);

stage4:mulbotblk PORT MAP(faout1,M(0),Q(2),c0,caryout4,P(2));
stage5:mulbotblk PORT MAP(faout2,M(1),Q(2),caryout4,caryout5,faout4);
stage6:mulbotblk PORT MAP(faout3,M(2),Q(2),caryout5,caryout6,faout5);
stage7:mulbotblk PORT MAP(stg1cary,M(3),Q(2),caryout6,stg2cary,faout6);

stage8:mulbotblk PORT MAP(faout4,M(0),Q(3),c0,caryout8,P(3));
stage9:mulbotblk PORT MAP(faout5,M(1),Q(3),caryout8,caryout9,P(4));
stage10:mulbotblk PORT MAP(faout6,M(2),Q(3),caryout9,caryout10,P(5));
stage11:mulbotblk PORT MAP(stg2cary,M(3),Q(3),caryout10,P(7),P(6));

end Behavioral;

